portable_atomic/gen/
utils.rs

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1// SPDX-License-Identifier: Apache-2.0 OR MIT
2// This file is @generated by target_spec.sh.
3// It is not intended for manual editing.
4
5#![allow(unused_macros)]
6
7// On AArch64, the base register of memory-related instructions must be 64-bit.
8// Passing a 32-bit value to `in(reg)` on AArch64 results in the upper bits
9// having an undefined value, but to work correctly with ILP32 ABI, the upper
10// bits must be zero, which is handled here by casting to u64. Another way to
11// handle this is to pass it as a pointer and clear the upper bits inside asm,
12// but it is easier to overlook than cast, which can catch overlooks by
13// asm_sub_register lint.
14// See also https://github.com/ARM-software/abi-aa/blob/2024Q3/aapcs64/aapcs64.rst#pointers
15//
16// Except for x86_64, which can use 32-bit registers in the destination operand
17// (on x86_64, we use the ptr_modifier macro to handle this), we need to do the
18// same for ILP32 ABI on other 64-bit architectures. (At least, as far as I can
19// see from the assembly generated by LLVM, this is also required for MIPS64 N32
20// ABI. I don't know about the RISC-V RV64ILP32* ABI, but in any case, this
21// should be a safe default for such ABIs).
22//
23// Known architectures that have such ABI are x86_64 (X32), AArch64 (ILP32),
24// mips64 (N32), and riscv64 (RV64ILP32*). (As of 2025-01-23, only the former
25// two are supported by rustc.) However, we list all known 64-bit architectures
26// because similar ABIs may exist or future added for other architectures.
27#[cfg(all(
28    target_pointer_width = "32",
29    any(
30        target_arch = "aarch64",
31        target_arch = "amdgpu",
32        target_arch = "arm64ec",
33        target_arch = "bpf",
34        target_arch = "loongarch64",
35        target_arch = "mips64",
36        target_arch = "mips64r6",
37        target_arch = "nvptx64",
38        target_arch = "powerpc64",
39        target_arch = "riscv64",
40        target_arch = "s390x",
41        target_arch = "sparc64",
42        target_arch = "wasm64",
43        target_arch = "x86_64",
44    ),
45))]
46#[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))]
47macro_rules! ptr_reg {
48    ($ptr:ident) => {{
49        let _: *const _ = $ptr; // ensure $ptr is a pointer (*mut _ or *const _)
50        #[cfg(not(portable_atomic_no_asm_maybe_uninit))]
51        #[allow(clippy::ptr_as_ptr)]
52        {
53            // If we cast to u64 here, the provenance will be lost,
54            // so we convert to MaybeUninit<u64> via zero extend helper.
55            crate::utils::zero_extend64_ptr($ptr as *mut ())
56        }
57        #[cfg(portable_atomic_no_asm_maybe_uninit)]
58        {
59            // Use cast on old rustc because it does not support MaybeUninit
60            // registers. This is still permissive-provenance compatible and
61            // is sound.
62            $ptr as u64
63        }
64    }};
65}
66#[cfg(not(all(
67    target_pointer_width = "32",
68    any(
69        target_arch = "aarch64",
70        target_arch = "amdgpu",
71        target_arch = "arm64ec",
72        target_arch = "bpf",
73        target_arch = "loongarch64",
74        target_arch = "mips64",
75        target_arch = "mips64r6",
76        target_arch = "nvptx64",
77        target_arch = "powerpc64",
78        target_arch = "riscv64",
79        target_arch = "s390x",
80        target_arch = "sparc64",
81        target_arch = "wasm64",
82        target_arch = "x86_64",
83    ),
84)))]
85#[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))]
86macro_rules! ptr_reg {
87    ($ptr:ident) => {{
88        let _: *const _ = $ptr; // ensure $ptr is a pointer (*mut _ or *const _)
89        $ptr // cast is unnecessary here.
90    }};
91}
92
93// Some 64-bit architectures have ABI with 32-bit pointer width (e.g., x86_64 X32 ABI,
94// AArch64 ILP32 ABI, MIPS64 N32 ABI). On those targets, AtomicU64 is available
95// and fast, so use it to implement normal sequence lock.
96//
97// See ptr_reg macro for the reason why all known 64-bit architectures are listed.
98#[cfg(any(
99    not(any(target_pointer_width = "16", target_pointer_width = "32")), // i.e., 64-bit or greater
100    target_arch = "aarch64",
101    target_arch = "amdgpu",
102    target_arch = "arm64ec",
103    target_arch = "bpf",
104    target_arch = "loongarch64",
105    target_arch = "mips64",
106    target_arch = "mips64r6",
107    target_arch = "nvptx64",
108    target_arch = "powerpc64",
109    target_arch = "riscv64",
110    target_arch = "s390x",
111    target_arch = "sparc64",
112    target_arch = "wasm64",
113    target_arch = "x86_64",
114))]
115#[macro_use]
116mod fast_atomic_64_macros {
117    macro_rules! cfg_has_fast_atomic_64 {
118        ($($tt:tt)*) => {
119            $($tt)*
120        };
121    }
122    macro_rules! cfg_no_fast_atomic_64 {
123        ($($tt:tt)*) => {};
124    }
125}
126#[cfg(not(any(
127    not(any(target_pointer_width = "16", target_pointer_width = "32")), // i.e., 64-bit or greater
128    target_arch = "aarch64",
129    target_arch = "amdgpu",
130    target_arch = "arm64ec",
131    target_arch = "bpf",
132    target_arch = "loongarch64",
133    target_arch = "mips64",
134    target_arch = "mips64r6",
135    target_arch = "nvptx64",
136    target_arch = "powerpc64",
137    target_arch = "riscv64",
138    target_arch = "s390x",
139    target_arch = "sparc64",
140    target_arch = "wasm64",
141    target_arch = "x86_64",
142)))]
143#[macro_use]
144mod fast_atomic_64_macros {
145    macro_rules! cfg_has_fast_atomic_64 {
146        ($($tt:tt)*) => {};
147    }
148    macro_rules! cfg_no_fast_atomic_64 {
149        ($($tt:tt)*) => {
150            $($tt)*
151        };
152    }
153}
portable_atomic/gen/utils.rs

portable_atomic/gen/
utils.rs
